Many IP cores especially from Xilinx have an AXI interface from ARM.
The AXI interface standard is free for download (after registration), but I don't think it's free for implementation. So I assume Xilinx has bought an AMBA license to equip its IP cores with AXI interfaces.
I don't have such license.
Can I offer AXI interfaces for my (open source) IP cores written in VHDL or Verilog?
(I'm not sure if I'm allowed to copy the license text into this question for further reading... please ask, so I can improve my question.)
ARM is a fabless processor design house known for its ARM processors and System-on-Chip (SoC) solutions in mobile devices.
The ARM ecosystem uses the ARM bus architecture (AMBA) to connect the processor with its peripheral components via AXI, AXI-Lite, AXI-Stream, APB, ... busses.
IP cores are ready to use components, which describe hardware. An IP core could be compared to a software class. Each core has an interface comparable to an API. They can be delivered 'open' with source code or 'closed' as a netlist or even encrypted.